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Topic: Firmware für 0.6.3 (Read 4990 times)
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SP3OSJ
Guest
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Re:Firmware für 0.6.3
« Reply #15 on: 27. June 2019, 15:25:13 »
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The reason for the SPI wiring of the LCD is possibly the malfunction of many LCDs HY28B in parallel mode. More and more LCDs are widely out of specs and do not work with UHSDR...
vy 73
Andreas
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Hi
The HAOYU factory has written about the HY28B parallel 16bit LCD:
This is not a problem. do not worry. Your initialization code is the earliest. There's an BUG. Please use the new initialization code updates.
DeviceCode = LCD_ReadReg(0x0000); /* read LCD ID */
/* recognition different screen, use different Initialization */
if( DeviceCode == 0x9325 || DeviceCode == 0x9328 )
{
LCD_Code = ILI9325;
LCD_WriteReg(0xE5, 0x78F0); /* set SRAM internal timing */
LCD_WriteReg(0x01, 0x0100); /* set Driver Output Control */
LCD_WriteReg(0x02, 0x0700); /* set 1 line inversion */
LCD_WriteReg(0x03, 0x1030); /* set GRAM write direction and BGR=1 */
LCD_WriteReg(0x04, 0x0000); /* Resize register */
LCD_WriteReg(0x08, 0x0207); /* set the back porch and front porch */
LCD_WriteReg(0x09, 0x0000); /* set non-display area refresh cycle ISC[3:0] */
LCD_WriteReg(0x0A, 0x0000); /* FMARK function */
LCD_WriteReg(0x0C, 0x0000); /* RGB interface setting */
LCD_WriteReg(0x0D, 0x0000); /* Frame marker Position */
LCD_WriteReg(0x0F, 0x0000); /* RGB interface polarity */
/*************Power On sequence ****************/
LCD_WriteReg(0x10, 0x0000); /* SAP, BT[3:0], AP, DSTB, SLP, STB */
LCD_WriteReg(0x11, 0x0007); /* DC1[2:0], DC0[2:0], VC[2:0] */
LCD_WriteReg(0x12, 0x0000); /* VREG1OUT voltage */
LCD_WriteReg(0x13, 0x0000); /* VDV[4:0] for VCOM amplitude */
LCD_WriteReg(0x07, 0x0001);
delay_ms(200);
/* Dis-charge capacitor power voltage */
LCD_WriteReg(0x10, 0x1090); /* SAP, BT[3:0], AP, DSTB, SLP, STB */
LCD_WriteReg(0x11, 0x0227); /* Set DC1[2:0], DC0[2:0], VC[2:0] */
delay_ms(50); /* Delay 50ms */
LCD_WriteReg(0x12, 0x001F);
delay_ms(50); /* Delay 50ms */
LCD_WriteReg(0x13, 0x1500); /* VDV[4:0] for VCOM amplitude */
LCD_WriteReg(0x29, 0x0027); /* 04 VCM[5:0] for VCOMH */
LCD_WriteReg(0x2B, 0x000D); /* Set Frame Rate */
delay_ms(50); /* Delay 50ms */
LCD_WriteReg(0x20, 0x0000); /* GRAM horizontal Address */
LCD_WriteReg(0x21, 0x0000); /* GRAM Vertical Address */
/* ----------- Adjust the Gamma Curve ---------- */
LCD_WriteReg(0x30, 0x0000);
LCD_WriteReg(0x31, 0x0707);
LCD_WriteReg(0x32, 0x0307);
LCD_WriteReg(0x35, 0x0200);
LCD_WriteReg(0x36, 0x0008);
LCD_WriteReg(0x37, 0x0004);
LCD_WriteReg(0x38, 0x0000);
LCD_WriteReg(0x39, 0x0707);
LCD_WriteReg(0x3C, 0x0002);
LCD_WriteReg(0x3D, 0x1D04);
/* ------------------ Set GRAM area --------------- */
LCD_WriteReg(0x50, 0x0000); /* Horizontal GRAM Start Address */
LCD_WriteReg(0x51, 0x00EF); /* Horizontal GRAM End Address */
LCD_WriteReg(0x52, 0x0000); /* Vertical GRAM Start Address */
LCD_WriteReg(0x53, 0x013F); /* Vertical GRAM Start Address */
LCD_WriteReg(0x60, 0xA700); /* Gate Scan Line */
LCD_WriteReg(0x61, 0x0001); /* NDL,VLE, REV */
LCD_WriteReg(0x6A, 0x0000); /* set scrolling line */
/* -------------- Partial Display Control --------- */
LCD_WriteReg(0x80, 0x0000);
LCD_WriteReg(0x81, 0x0000);
LCD_WriteReg(0x82, 0x0000);
LCD_WriteReg(0x83, 0x0000);
LCD_WriteReg(0x84, 0x0000);
LCD_WriteReg(0x85, 0x0000);
/* -------------- Panel Control ------------------- */
LCD_WriteReg(0x90, 0x0010);
LCD_WriteReg(0x92, 0x0600);
LCD_WriteReg(0x07, 0x0133); /* 262K color and display ON */
}
We tested one by one before shipment. Usually only some LCDs have damaged pixels (bright pixels).As you said so many bad LCDs, then we have already closed down.This is not going to happen. The truth is.
This is a problem with your LCD driver. We have three models of the 2.8LCD 9325 controller. They are ILI9325A ILI9325C and ILI9325D. Their operation timing is different. The A version is the slowest. The D version is the fastest. So the timing of the operation of your LCD driver must be done in accordance with the A version. In addition, the D version must also use the new initialization code. I will attach a new initialization code later.
This is compatible with all 2.8 LCDs. (The timing mentioned above refers to the address setup time/address hold time of the i8080 bus, and the data setup time/data hold time. Different MCU settings are different. You can modify this part of the timing.)
73
Artur
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DB4PLE
positron
Urgestein
 Offline
Posts: 1278
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Re:Firmware für 0.6.3
« Reply #18 on: 30. June 2019, 13:25:12 »
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Hi Artur,
it would be very helpful if you could identify the settings which make the difference for your displays.
In your quote below I removed all settings which should not be relevant.
So what you have to do know is to use the existing UHSDR firmware source code, and try to replace existing values for the 9325
with the ones below.
We have in the source code basically the same sequence of settings and it is easy to find where to replace
the values.
The idea is to find which values have an influence and which not.
Only then we can start thinking about merging the settings (or not). And without access to your displays, we can't do this.
Some of these settings are voltage/drive current related. As far as I could see it, the UHSDR code uses
fairly safe (read strong) settings for the drive settings. So these are not necessarily the first targets. But one never knows.
73
Danilo
The HAOYU factory has written about the HY28B parallel 16bit LCD:
This is not a problem. do not worry. Your initialization code is the earliest. There's an BUG. Please use the new initialization code updates.
DeviceCode = LCD_ReadReg(0x0000); /* read LCD ID */
/* recognition different screen, use different Initialization */
if( DeviceCode == 0x9325 || DeviceCode == 0x9328 )
{
LCD_Code = ILI9325;
LCD_WriteReg(0xE5, 0x78F0); /* set SRAM internal timing */
LCD_WriteReg(0x01, 0x0100); /* set Driver Output Control */
LCD_WriteReg(0x02, 0x0700); /* set 1 line inversion */
LCD_WriteReg(0x03, 0x1030); /* set GRAM write direction and BGR=1 */
...
LCD_WriteReg(0x08, 0x0207); /* set the back porch and front porch */
...
/*************Power On sequence ****************/
LCD_WriteReg(0x10, 0x0000); /* SAP, BT[3:0], AP, DSTB, SLP, STB */
LCD_WriteReg(0x11, 0x0007); /* DC1[2:0], DC0[2:0], VC[2:0] */
LCD_WriteReg(0x12, 0x0000); /* VREG1OUT voltage */
LCD_WriteReg(0x13, 0x0000); /* VDV[4:0] for VCOM amplitude */
LCD_WriteReg(0x07, 0x0001);
delay_ms(200);
/* Dis-charge capacitor power voltage */
LCD_WriteReg(0x10, 0x1090); /* SAP, BT[3:0], AP, DSTB, SLP, STB */
LCD_WriteReg(0x11, 0x0227); /* Set DC1[2:0], DC0[2:0], VC[2:0] */
delay_ms(50); /* Delay 50ms */
LCD_WriteReg(0x12, 0x001F);
delay_ms(50); /* Delay 50ms */
LCD_WriteReg(0x13, 0x1500); /* VDV[4:0] for VCOM amplitude */
LCD_WriteReg(0x29, 0x0027); /* 04 VCM[5:0] for VCOMH */
LCD_WriteReg(0x2B, 0x000D); /* Set Frame Rate */
delay_ms(50); /* Delay 50ms */
...
/* -------------- Panel Control ------------------- */
...
LCD_WriteReg(0x92, 0x0600);
...
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