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SP9BSL
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alter Hase
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Re:DDC Module2
« Reply #2 on: 12. August 2020, 17:28:19 »
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Yes, it's pity that he doesn't provide the schematics. Looks like he is comfortable developing this way.
Cyclone 10 is fairly new chip, although not a big step in technology compared to Cyclone IV, and really not a big advantage looking at the prices (or clones).
Edit:
It is interesting if the board supports the 6m band because of low maximum ADC sample clock. Also there is lack of low phase noise clock. The chip capacity is too low for two receivers working simultaneously but this is minor issue, the chip can be migrated to higher density easily...
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| « Last Edit: 12. August 2020, 17:49:19 by SP9BSL » |
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73 Slawek
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SP9BSL
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alter Hase
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Re:DDC Module2
« Reply #3 on: 13. August 2020, 08:09:51 »
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Hi,
looks like Rolin will have "own" version of UI (the citation from Russian forum):
" And so far everything is complicated with software, I have never coded in C ++, and even under STM32. So far I decided to make my own version of the Sparrow 4 printed circuit board, where the module will be normally installed, the power is normally done and what would be with the batteries inside.
So if there are enthusiastic specialists here who can "trick" over the UHSDR firmware, you can collaborate.
All you need to do is:
1) - disable checking and displaying an error on the screen at startup for SI570, quadrature audio codec and micro thermometer
2) - remake the I2C control function of the quadrature audio code to control the module.
3) - to remake the DSP to work at zero IF."
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73 Slawek
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SP9BSL
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alter Hase
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Re:DDC Module2
« Reply #5 on: 13. August 2020, 09:58:43 »
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The boards runs as slave, simply replacing the RX/TX codec (i assume this from the description) - this is different approach to our. So there must be a sync code in FPGA to align two clocks - the FPGA and the Masterclock from STM. I did not dig in the fpga code yet but this must be tricky or there will be audible clicks.
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73 Slawek
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BO_Andy
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Ich bin schon Groß und kann Alleine Laufen
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Re:DDC Module2
« Reply #7 on: 24. August 2020, 17:47:25 »
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Ich würde mich glatt dazu nochma breit schalten lassen 10 PcBs in Gold zu bestellen
LG BO_Andy
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BO_Andy
Urgestein
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Ich bin schon Groß und kann Alleine Laufen
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Re:DDC Module2
« Reply #8 on: 25. August 2020, 17:26:26 »
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Das gefällt mir denn würde ich auch noch bauen sobald es denn pcb Satz gibt
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SP9BSL
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Re:DDC Module2
« Reply #9 on: 26. August 2020, 06:34:43 »
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Hi,
some remarks looking at all of this - I don't know if David looks here but if you guys have problem with UHSDR - why don't you prepare the FPGA code to be seen as SI570 on I2C by STM?
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| « Last Edit: 26. August 2020, 06:36:51 by SP9BSL » |
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73 Slawek
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SP9BSL
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Re:DDC Module2
« Reply #11 on: 26. August 2020, 07:09:48 »
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Hi Andreas,
of course, the identification is ready with SParkle (in upcoming pull request), but I use SPI... Also there is control for amplifier/attenuator with callback function - just need to define it in the specyfic hardware code.
Side question caused by lack of schematics, maybe someone knows - is there a JTAG for fpga on the David's pcb?
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| « Last Edit: 26. August 2020, 07:11:58 by SP9BSL » |
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73 Slawek
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Author
... Also muss Google helfen.
