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Topic: about the maths in the FPGA (Read 2684 times)
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SP9BSL
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alter Hase
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Re:about the maths in the FPGA
« Reply #1 on: 17. May 2019, 11:25:58 »
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Hi Andreas,
the divided FIR filter is mainly because of less computation needed when we filter in multiple stages with wider bandwidth than in single, also the group delay is smaller because of shorter filter kernel.
Could you provide link to the place where the Red Pitaya algorithm is described? I do not see CORDIC implementation on the schematics you showed.
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| « Last Edit: 17. May 2019, 11:26:25 by SP9BSL » |
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73 Slawek
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SP9BSL
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alter Hase
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Re:about the maths in the FPGA
« Reply #3 on: 17. May 2019, 11:44:37 »
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Thank you Andreas,
with 125MHz sampling clock there is mismatch in decimated sample rate compared to "normal" audio sample rate, thus divided FIR filter acts as a sample rate converter which results in 48kHz data output instead of 50kHz what would be expected without this conversion. Therefore I use 122.88MHz sample clock to easy decimate to 48/96/192kHz. The rest is as you mention Frank's knowledge 
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| « Last Edit: 17. May 2019, 11:50:50 by SP9BSL » |
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73 Slawek
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DD4WH
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alter Hase
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Ich liebe dieses Forum!
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Re:about the maths in the FPGA
« Reply #5 on: 17. May 2019, 14:50:14 »
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Hi Andres and Slawek,
well, I know merely nothing about FPGA and DDC radio . . . but I try to summarize some of my basic DSP experience here:
* the filters are only necessary because you need a good lowpass filter before a downsampling step [lowpass filter PLUS downsampling = decimation]
* the CIC does not have a nice frequency response, that is why a subsequent FIR compensation filter is often used (chapter 10.14 in Lyons 2011).
* as far as I know, the FIR decimation stages, but also the CIC decimation stages are divided into decimate-by-two stages, because it is much faster to decimate step-by-step --> see chapter 10.2 on multistage decimation in Lyons 2011
* maybe the use of polyphase CIC / FIR filters would be wise in order to save processor time (chapter 13.24 in Lyons 2011)
* or also halfband-FIR filters, but I have never used these yet
* my recommendation for further reading about these things would be:
Whiteley 2011 [CIC implementation etc.]
Lyons 2011 [absolute must for DSP !]
https://github.com/DD4WH/Teensy-ConvolutionSDR/wiki/Links-&-Resources
But there are so many others that have written FPGA code for SDR, that it could save a lot of time to have a look into their code.
Best 73s
Frank
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| « Last Edit: 17. May 2019, 14:56:34 by DD4WH » |
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Teensy Convolution SDR
https://github.com/DD4WH/Teensy-ConvolutionSDR
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SP9BSL
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alter Hase
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Re:about the maths in the FPGA
« Reply #6 on: 17. May 2019, 19:46:55 »
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Hi Frank,
thanks for the answer, I agree: Lyons is the absolute basis, I have it of course, since 2001 (the first edition). After this book I recommend the marvelous free dspguide.com, and dspguru (mentioned in red pitaya notes).
@Andreas:
The ready code for ddc/duc conversion: I use the N2ADR code and recommend this for analysis (look at the N7DCC - D.Fainitski github pages in part related to module1 and Odyssey SDR). It has been written in Verilog.
The CORDIC algorithm FAQ: https://dspguru.com/dsp/faqs/cordic/.
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| « Last Edit: 17. May 2019, 19:51:27 by SP9BSL » |
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73 Slawek
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DD4WH
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alter Hase
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Ich liebe dieses Forum!
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Re:about the maths in the FPGA
« Reply #8 on: 18. May 2019, 09:41:24 »
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Hi Slawek,
thanks for the info! I never understood what CORDIC exactly is, but your link helped me to figure it out! Thanks!
73 Frank
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Teensy Convolution SDR
https://github.com/DD4WH/Teensy-ConvolutionSDR
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. It is an amazing thing.
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